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fpga_admissionwebhook: update resource names

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This commit is contained in:
Dmitry Rozhkov 2018-07-19 11:26:14 +03:00
parent 1e7dbac162
commit 972a80bedb
3 changed files with 30 additions and 30 deletions
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2
cmd/fpga_admissionwebhook/README.md
View File

@ -41,7 +41,7 @@ Then run the script `scripts/webhook-deploy.sh`.
By default the script deploys the webhook in the preprogrammed mode (when By default the script deploys the webhook in the preprogrammed mode (when
requested FPGA resources get translated to AF resources, e.g. requested FPGA resources get translated to AF resources, e.g.
"intel.com/fpga-arria10-nlb0" -> "intel.com/fpga-af-d8424dc4a4a3c413f89e433683f9040b"). "fpga.intel.com/arria10-nlb0" -> "fpga.intel.com/af-d8424dc4a4a3c413f89e433683f9040b").
You can command the script to deploy the webhook in the orchestrated mode with You can command the script to deploy the webhook in the orchestrated mode with
the option `--mode`. the option `--mode`.

18
cmd/fpga_admissionwebhook/fpga_admissionwebhook.go
View File

@ -65,7 +65,7 @@ var (
scheme = runtime.NewScheme() scheme = runtime.NewScheme()
codecs = serializer.NewCodecFactory(scheme) codecs = serializer.NewCodecFactory(scheme)
rfc6901Escaper = strings.NewReplacer("~", "~0", "/", "~1") rfc6901Escaper = strings.NewReplacer("~", "~0", "/", "~1")
resourceRe = regexp.MustCompile(`intel.com/fpga-(?P<Region>[[:alnum:]]+)(-(?P<Af>[[:alnum:]]+))?`) resourceRe = regexp.MustCompile(`fpga.intel.com/(?P<Region>[[:alnum:]]+)(-(?P<Af>[[:alnum:]]+))?`)
) )
func init() { func init() {
@ -130,12 +130,12 @@ func parseResourceName(input string) (string, string, error) {
// TODO: get rid of hardcoded translations of FPGA resource names to region interface IDs // TODO: get rid of hardcoded translations of FPGA resource names to region interface IDs
func translateFpgaResourceName(oldname corev1.ResourceName) string { func translateFpgaResourceName(oldname corev1.ResourceName) string {
switch strings.ToLower(string(oldname)) { switch strings.ToLower(string(oldname)) {
case "intel.com/fpga-arria10": case "fpga.intel.com/arria10":
return rfc6901Escaper.Replace("intel.com/fpga-region-ce48969398f05f33946d560708be108a") return rfc6901Escaper.Replace("fpga.intel.com/region-ce48969398f05f33946d560708be108a")
case "intel.com/fpga-arria10-nlb0": case "fpga.intel.com/arria10-nlb0":
return rfc6901Escaper.Replace("intel.com/fpga-af-d8424dc4a4a3c413f89e433683f9040b") return rfc6901Escaper.Replace("fpga.intel.com/af-d8424dc4a4a3c413f89e433683f9040b")
case "intel.com/fpga-arria10-nlb3": case "fpga.intel.com/arria10-nlb3":
return rfc6901Escaper.Replace("intel.com/fpga-af-f7df405cbd7acf7222f144b0b93acd18") return rfc6901Escaper.Replace("fpga.intel.com/af-f7df405cbd7acf7222f144b0b93acd18")
} }
return "" return ""
@ -215,7 +215,7 @@ func getPatchOpsOrchestrated(containerIdx int, container corev1.Container) ([]st
} }
op := fmt.Sprintf(resourceReplaceOp, containerIdx, "limits", rfc6901Escaper.Replace(string(resourceName)), op := fmt.Sprintf(resourceReplaceOp, containerIdx, "limits", rfc6901Escaper.Replace(string(resourceName)),
containerIdx, "limits", rfc6901Escaper.Replace("intel.com/fpga-region-"+interfaceID), resourceQuantity.String()) containerIdx, "limits", rfc6901Escaper.Replace("fpga.intel.com/region-"+interfaceID), resourceQuantity.String())
ops = append(ops, op) ops = append(ops, op)
oldVars, err := getEnvVars(container) oldVars, err := getEnvVars(container)
@ -243,7 +243,7 @@ func getPatchOpsOrchestrated(containerIdx int, container corev1.Container) ([]st
} }
op := fmt.Sprintf(resourceReplaceOp, containerIdx, "requests", rfc6901Escaper.Replace(string(resourceName)), op := fmt.Sprintf(resourceReplaceOp, containerIdx, "requests", rfc6901Escaper.Replace(string(resourceName)),
containerIdx, "requests", rfc6901Escaper.Replace("intel.com/fpga-region-"+interfaceID), resourceQuantity.String()) containerIdx, "requests", rfc6901Escaper.Replace("fpga.intel.com/region-"+interfaceID), resourceQuantity.String())
ops = append(ops, op) ops = append(ops, op)
mutated = true mutated = true
} }

40
cmd/fpga_admissionwebhook/fpga_admissionwebhook_test.go
View File

@ -39,23 +39,23 @@ func TestParseResourceName(t *testing.T) {
expectedErr bool expectedErr bool
}{ }{
{ {
input: "intel.com/fpga-arria10", input: "fpga.intel.com/arria10",
expectedErr: true, expectedErr: true,
}, },
{ {
input: "intel.com/fpga-unknown", input: "fpga.intel.com/unknown",
expectedErr: true, expectedErr: true,
}, },
{ {
input: "example.com/fpga-something", input: "fpga.example.com/something",
}, },
{ {
input: "intel.com/fpga-arria10-nlb0", input: "fpga.intel.com/arria10-nlb0",
interfaceID: "ce48969398f05f33946d560708be108a", interfaceID: "ce48969398f05f33946d560708be108a",
afuID: "d8424dc4a4a3c413f89e433683f9040b", afuID: "d8424dc4a4a3c413f89e433683f9040b",
}, },
{ {
input: "intel.com/fpga-arria10-nlb3", input: "fpga.intel.com/arria10-nlb3",
interfaceID: "ce48969398f05f33946d560708be108a", interfaceID: "ce48969398f05f33946d560708be108a",
afuID: "f7df405cbd7acf7222f144b0b93acd18", afuID: "f7df405cbd7acf7222f144b0b93acd18",
}, },
@ -88,11 +88,11 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"intel.com/fpga-arria10-nlb0": resource.MustParse("1"), "fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
"cpu": resource.MustParse("1"), "cpu": resource.MustParse("1"),
}, },
Requests: corev1.ResourceList{ Requests: corev1.ResourceList{
"intel.com/fpga-arria10-nlb0": resource.MustParse("1"), "fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
"cpu": resource.MustParse("1"), "cpu": resource.MustParse("1"),
}, },
}, },
@ -104,8 +104,8 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"intel.com/fpga-arria10-nlb0": resource.MustParse("1"), "fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
"intel.com/fpga-arria10-nlb3": resource.MustParse("1"), "fpga.intel.com/arria10-nlb3": resource.MustParse("1"),
}, },
}, },
}, },
@ -116,8 +116,8 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Requests: corev1.ResourceList{ Requests: corev1.ResourceList{
"intel.com/fpga-arria10-nlb0": resource.MustParse("1"), "fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
"intel.com/fpga-arria10-nlb3": resource.MustParse("1"), "fpga.intel.com/arria10-nlb3": resource.MustParse("1"),
}, },
}, },
}, },
@ -128,7 +128,7 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Requests: corev1.ResourceList{ Requests: corev1.ResourceList{
"intel.com/fpga-unknown-nlb0": resource.MustParse("1"), "fpga.intel.com/unknown-nlb0": resource.MustParse("1"),
}, },
}, },
}, },
@ -139,7 +139,7 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Requests: corev1.ResourceList{ Requests: corev1.ResourceList{
"intel.com/fpga-arria10-unknown": resource.MustParse("1"), "fpga.intel.com/arria10-unknown": resource.MustParse("1"),
}, },
}, },
}, },
@ -150,7 +150,7 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"intel.com/fpga-unknown-nlb0": resource.MustParse("1"), "fpga.intel.com/unknown-nlb0": resource.MustParse("1"),
}, },
}, },
}, },
@ -161,7 +161,7 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"intel.com/fpga-arria10-unknown": resource.MustParse("1"), "fpga.intel.com/arria10-unknown": resource.MustParse("1"),
}, },
}, },
}, },
@ -172,7 +172,7 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
container: corev1.Container{ container: corev1.Container{
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"intel.com/fpga-arria10-nlb0": resource.MustParse("1"), "fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
}, },
}, },
Env: []corev1.EnvVar{ Env: []corev1.EnvVar{
@ -295,11 +295,11 @@ func TestMutatePods(t *testing.T) {
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"cpu": resource.MustParse("1"), "cpu": resource.MustParse("1"),
"intel.com/fpga-arria10": resource.MustParse("1"), "fpga.intel.com/arria10": resource.MustParse("1"),
}, },
Requests: corev1.ResourceList{ Requests: corev1.ResourceList{
"cpu": resource.MustParse("1"), "cpu": resource.MustParse("1"),
"intel.com/fpga-arria10": resource.MustParse("1"), "fpga.intel.com/arria10": resource.MustParse("1"),
}, },
}, },
}, },
@ -457,11 +457,11 @@ func TestGetEnvVars(t *testing.T) {
Resources: corev1.ResourceRequirements{ Resources: corev1.ResourceRequirements{
Limits: corev1.ResourceList{ Limits: corev1.ResourceList{
"cpu": resource.MustParse("1"), "cpu": resource.MustParse("1"),
"intel.com/fpga-arria10": resource.MustParse("1"), "fpga.intel.com/arria10": resource.MustParse("1"),
}, },
Requests: corev1.ResourceList{ Requests: corev1.ResourceList{
"cpu": resource.MustParse("1"), "cpu": resource.MustParse("1"),
"intel.com/fpga-arria10": resource.MustParse("1"), "fpga.intel.com/arria10": resource.MustParse("1"),
}, },
}, },
Env: []corev1.EnvVar{ Env: []corev1.EnvVar{