diff --git a/cmd/fpga_admissionwebhook/fpga_admissionwebhook_test.go b/cmd/fpga_admissionwebhook/fpga_admissionwebhook_test.go
index 32dce0e4..312ef4fb 100644
--- a/cmd/fpga_admissionwebhook/fpga_admissionwebhook_test.go
+++ b/cmd/fpga_admissionwebhook/fpga_admissionwebhook_test.go
@@ -130,11 +130,11 @@ func TestMutatePods(t *testing.T) {
 					Image: "test-image",
 					Resources: corev1.ResourceRequirements{
 						Limits: corev1.ResourceList{
-							"cpu": resource.MustParse("1"),
+							"cpu":                    resource.MustParse("1"),
 							"fpga.intel.com/arria10": resource.MustParse("1"),
 						},
 						Requests: corev1.ResourceList{
-							"cpu": resource.MustParse("1"),
+							"cpu":                    resource.MustParse("1"),
 							"fpga.intel.com/arria10": resource.MustParse("1"),
 						},
 					},
diff --git a/cmd/fpga_admissionwebhook/patcher_test.go b/cmd/fpga_admissionwebhook/patcher_test.go
index 05b0247b..56e5367f 100644
--- a/cmd/fpga_admissionwebhook/patcher_test.go
+++ b/cmd/fpga_admissionwebhook/patcher_test.go
@@ -90,7 +90,7 @@ func TestGetPatchOpsPreprogrammed(t *testing.T) {
 				Resources: corev1.ResourceRequirements{
 					Limits: corev1.ResourceList{
 						"fpga.intel.com/arria10-unknown": resource.MustParse("1"),
-						"cpu": resource.MustParse("1"),
+						"cpu":                            resource.MustParse("1"),
 					},
 				},
 			},
@@ -102,7 +102,7 @@ func TestGetPatchOpsPreprogrammed(t *testing.T) {
 				Resources: corev1.ResourceRequirements{
 					Requests: corev1.ResourceList{
 						"fpga.intel.com/arria10-unknown": resource.MustParse("1"),
-						"cpu": resource.MustParse("1"),
+						"cpu":                            resource.MustParse("1"),
 					},
 				},
 			},
@@ -114,11 +114,11 @@ func TestGetPatchOpsPreprogrammed(t *testing.T) {
 				Resources: corev1.ResourceRequirements{
 					Limits: corev1.ResourceList{
 						"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
-						"cpu": resource.MustParse("1"),
+						"cpu":                         resource.MustParse("1"),
 					},
 					Requests: corev1.ResourceList{
 						"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
-						"cpu": resource.MustParse("1"),
+						"cpu":                         resource.MustParse("1"),
 					},
 				},
 			},
@@ -222,11 +222,11 @@ func TestGetPatchOpsOrchestrated(t *testing.T) {
 				Resources: corev1.ResourceRequirements{
 					Limits: corev1.ResourceList{
 						"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
-						"cpu": resource.MustParse("1"),
+						"cpu":                         resource.MustParse("1"),
 					},
 					Requests: corev1.ResourceList{
 						"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
-						"cpu": resource.MustParse("1"),
+						"cpu":                         resource.MustParse("1"),
 					},
 				},
 				Env: []corev1.EnvVar{