Currently we have hardcoded mapping from human readable names of
AFs and FPGA regions like arria10-nlb0 to the resource names
produced by the FPGA device plugin. This is not sustainable
long term solution.
Implement CRD based mappings so that a new mapping can be added or
removed dynamically by cluster admins with CRD resources.
In `orchestrated` mode the webhook parses requested resources and to translates
them to a container's ENV variables to let CRI hooks to program the FPGA with
requested bitstreams before starting the container.
