mirror of
https://github.com/intel/intel-device-plugins-for-kubernetes.git
synced 2025-06-03 03:59:37 +00:00
d7997800a9
klog has added ktesting/textlogger and is going to deprecate klogr. The deprecation is going to trigger golangci-lint (staticcheck) errors so rework the logging and move to ktesting/textlogger. The commit also fixes the loglevel setting with operator. Signed-off-by: Mikko Ylinen <mikko.ylinen@intel.com>
521 lines
14 KiB
Go
521 lines
14 KiB
Go
// Copyright 2018 Intel Corporation. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package patcher
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import (
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"reflect"
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"testing"
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corev1 "k8s.io/api/core/v1"
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"k8s.io/apimachinery/pkg/api/resource"
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metav1 "k8s.io/apimachinery/pkg/apis/meta/v1"
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ctrl "sigs.k8s.io/controller-runtime"
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fpgav2 "github.com/intel/intel-device-plugins-for-kubernetes/pkg/apis/fpga/v2"
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"k8s.io/klog/v2/ktesting"
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)
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func checkExpectedError(t *testing.T, expectedErr bool, err error, testName string) {
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t.Helper()
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if expectedErr && err == nil {
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t.Errorf("Test case '%s': no error returned", testName)
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}
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if !expectedErr && err != nil {
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t.Errorf("Test case '%s': unexpected error: %+v", testName, err)
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}
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}
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func TestPatcherStorageFunctions(t *testing.T) {
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goodAf := &fpgav2.AcceleratorFunction{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: af,
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},
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}
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brokenAf := &fpgav2.AcceleratorFunction{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "wrong string",
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InterfaceID: "wrong string",
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Mode: af,
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},
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}
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region := &fpgav2.FpgaRegion{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10",
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},
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Spec: fpgav2.FpgaRegionSpec{
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InterfaceID: "ce48969398f05f33946d560708be108a",
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},
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}
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regionAlias := &fpgav2.FpgaRegion{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-alias",
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},
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Spec: fpgav2.FpgaRegionSpec{
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InterfaceID: "ce48969398f05f33946d560708be108a",
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},
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}
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tcases := []struct {
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name string
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afsToAdd []*fpgav2.AcceleratorFunction
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afsToRemove []*fpgav2.AcceleratorFunction
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regionsToAdd []*fpgav2.FpgaRegion
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regionsToRemove []*fpgav2.FpgaRegion
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expectedResourceModeMapSize int
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expectedResourceMapSize int
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expectedIdentitySetSize int
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expectedErr bool
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}{
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{
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name: "Add one good af",
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afsToAdd: []*fpgav2.AcceleratorFunction{goodAf},
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expectedResourceModeMapSize: 1,
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expectedResourceMapSize: 1,
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expectedIdentitySetSize: 1,
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},
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{
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name: "Add one broken af",
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afsToAdd: []*fpgav2.AcceleratorFunction{brokenAf},
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expectedErr: true,
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},
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{
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name: "Add one and remove one good af",
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afsToAdd: []*fpgav2.AcceleratorFunction{goodAf},
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afsToRemove: []*fpgav2.AcceleratorFunction{goodAf},
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},
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{
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name: "Add one good region",
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regionsToAdd: []*fpgav2.FpgaRegion{region},
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expectedResourceModeMapSize: 1,
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expectedResourceMapSize: 1,
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expectedIdentitySetSize: 1,
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},
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{
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name: "Add one and remove one good region",
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regionsToAdd: []*fpgav2.FpgaRegion{region},
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regionsToRemove: []*fpgav2.FpgaRegion{region},
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},
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{
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name: "Add one region and one alias then remove one alias",
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regionsToAdd: []*fpgav2.FpgaRegion{region, regionAlias},
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regionsToRemove: []*fpgav2.FpgaRegion{region},
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expectedResourceModeMapSize: 1,
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expectedResourceMapSize: 1,
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expectedIdentitySetSize: 1,
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},
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{
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name: "Add one region and one alias",
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regionsToAdd: []*fpgav2.FpgaRegion{region, regionAlias},
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expectedResourceModeMapSize: 2,
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expectedResourceMapSize: 2,
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expectedIdentitySetSize: 1,
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},
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{
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name: "Add one region and one alias then remove all",
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regionsToAdd: []*fpgav2.FpgaRegion{region, regionAlias},
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regionsToRemove: []*fpgav2.FpgaRegion{region, regionAlias},
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},
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}
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for _, tt := range tcases {
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t.Run(tt.name, func(t *testing.T) {
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logger, _ := ktesting.NewTestContext(t)
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p := newPatcher(logger)
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for _, af := range tt.afsToAdd {
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err := p.AddAf(af)
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checkExpectedError(t, tt.expectedErr, err, tt.name)
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}
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for _, reg := range tt.regionsToAdd {
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p.AddRegion(reg)
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}
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for _, af := range tt.afsToRemove {
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p.RemoveAf(af.Name)
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}
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for _, reg := range tt.regionsToRemove {
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p.RemoveRegion(reg.Name)
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}
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if tt.expectedResourceModeMapSize != len(p.resourceModeMap) {
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t.Errorf("wrong size of resourceModeMap. Expected %d, but got %d", tt.expectedResourceModeMapSize, len(p.resourceModeMap))
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}
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if tt.expectedResourceMapSize != len(p.resourceMap) {
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t.Errorf("wrong size of resourceMap. Expected %d, but got %d", tt.expectedResourceMapSize, len(p.resourceMap))
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}
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if tt.expectedIdentitySetSize != len(p.identitySet) {
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t.Errorf("wrong size of identitySet. Expected %d, but got %d", tt.expectedIdentitySetSize, len(p.identitySet))
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}
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})
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}
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}
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func TestSanitizeContainerEnv(t *testing.T) {
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tcases := []struct {
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name string
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container corev1.Container
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expectedContainer corev1.Container
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}{
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{
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name: "Container OK",
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container: corev1.Container{},
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expectedContainer: corev1.Container{},
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},
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{
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name: "Wrong ENV FPGA_AFU",
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container: corev1.Container{
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Env: []corev1.EnvVar{
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{
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Name: "FPGA_AFU",
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Value: "fake value",
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},
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},
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},
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expectedContainer: corev1.Container{},
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},
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{
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name: "Wrong ENV FPGA_REGION",
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container: corev1.Container{
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Env: []corev1.EnvVar{
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{
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Name: "FPGA_REGION",
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Value: "fake value",
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},
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},
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},
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expectedContainer: corev1.Container{},
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},
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{
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name: "Wrong ENV FPGA_REGION and unrelated env var",
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container: corev1.Container{
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Env: []corev1.EnvVar{
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{
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Name: "FPGA_REGION",
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Value: "fake value",
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},
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{
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Name: "FAKE_VAR",
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Value: "fake value",
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},
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},
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},
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expectedContainer: corev1.Container{
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Env: []corev1.EnvVar{
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{
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Name: "FAKE_VAR",
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Value: "fake value",
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},
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},
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},
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},
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}
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for _, tt := range tcases {
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t.Run(tt.name, func(t *testing.T) {
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c := sanitizeContainer(tt.container)
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if tt.expectedContainer.Env != nil && !reflect.DeepEqual(c.Env, tt.expectedContainer.Env) {
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t.Errorf("Got wrong container Env %+v instead of expected %+v", c.Env, tt.expectedContainer.Env)
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}
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if tt.expectedContainer.Env == nil && c.Env != nil {
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t.Errorf("Got wrong container Env %+v instead of expected 'nil'", c.Env)
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}
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})
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}
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}
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func TestGetPatchOps(t *testing.T) {
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tcases := []struct {
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name string
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container corev1.Container
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afs []*fpgav2.AcceleratorFunction
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regions []*fpgav2.FpgaRegion
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expectedErr bool
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expectedOps int
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}{
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{
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name: "Successful handling for region mode",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb0-alias": resource.MustParse("2"),
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"cpu": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb0-alias": resource.MustParse("2"),
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"cpu": resource.MustParse("3"),
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},
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},
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Env: []corev1.EnvVar{
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{
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Name: "SOME_VAR",
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Value: "fake value",
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},
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},
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},
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afs: []*fpgav2.AcceleratorFunction{
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: region,
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},
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},
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0-alias",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: region,
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},
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},
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},
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expectedOps: 7,
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},
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{
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name: "Successful handling for af mode",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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},
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},
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},
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afs: []*fpgav2.AcceleratorFunction{
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: af,
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},
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},
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},
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expectedOps: 4,
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},
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{
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name: "Skip handling for an identity mapping",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/af-ce4.d84.zkiWk5jwXzOUbVYHCL4QithCTcSko8QT-J5DNoP5BAs": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/af-ce4.d84.zkiWk5jwXzOUbVYHCL4QithCTcSko8QT-J5DNoP5BAs": resource.MustParse("1"),
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},
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},
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},
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afs: []*fpgav2.AcceleratorFunction{
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: af,
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},
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},
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0-alias",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: af,
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},
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},
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},
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},
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{
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name: "Successful handling for regiondevel mode",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10": resource.MustParse("1"),
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},
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},
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},
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regions: []*fpgav2.FpgaRegion{
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10",
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},
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Spec: fpgav2.FpgaRegionSpec{
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InterfaceID: "ce48969398f05f33946d560708be108a",
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},
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},
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},
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expectedOps: 4,
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},
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{
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name: "Unequal FPGA resources in Limits and Requests 1",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb3": resource.MustParse("2"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unequal FPGA resources in Limits and Requests 2",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb3": resource.MustParse("2"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unknown FPGA resources in container requirements",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Requests: corev1.ResourceList{
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"fpga.intel.com/unknown-nlb0": resource.MustParse("1"),
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},
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Limits: corev1.ResourceList{
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"fpga.intel.com/unknown-nlb0": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Wrong type of quantity",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1.1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1.1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Require resources operated in af and region modes",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb3": resource.MustParse("2"),
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"cpu": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb3": resource.MustParse("2"),
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"cpu": resource.MustParse("3"),
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},
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},
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},
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afs: []*fpgav2.AcceleratorFunction{
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: region,
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},
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},
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb3",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "f7df405cbd7acf7222f144b0b93acd18",
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Mode: af,
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unknown mode",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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},
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},
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},
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afs: []*fpgav2.AcceleratorFunction{
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{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav2.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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InterfaceID: "ce48969398f05f33946d560708be108a",
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Mode: "unknown",
|
|
},
|
|
},
|
|
},
|
|
expectedErr: true,
|
|
},
|
|
}
|
|
|
|
for _, tt := range tcases {
|
|
t.Run(tt.name, func(t *testing.T) {
|
|
p := newPatcher(ctrl.Log.WithName("test"))
|
|
for _, af := range tt.afs {
|
|
_ = p.AddAf(af)
|
|
}
|
|
for _, region := range tt.regions {
|
|
p.AddRegion(region)
|
|
}
|
|
ops, err := p.getPatchOps(0, tt.container)
|
|
checkExpectedError(t, tt.expectedErr, err, tt.name)
|
|
if len(ops) != tt.expectedOps {
|
|
t.Errorf("test case '%s': expected %d ops, but got %d\n%v", tt.name, tt.expectedOps, len(ops), ops)
|
|
}
|
|
})
|
|
}
|
|
}
|