mirror of
https://github.com/intel/intel-device-plugins-for-kubernetes.git
synced 2025-06-03 03:59:37 +00:00
70f862f2aa
In this initial commit the following checks are disabled due to excessive amount of changes required: - dupl (duplicate code) - funlen (function length) - goerr113 (errors handling expressions) - gomnd (magic numbers) - gosec (security) - nakedret (naked returns) - wsl (forces to use empty lines) - errcheck (checking for unchecked errors) - staticcheck (static analysis)
103 lines
2.6 KiB
Go
103 lines
2.6 KiB
Go
// Copyright 2019 Intel Corporation. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package bitstream
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import (
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"testing"
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)
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func TestGetFPGABitstream(t *testing.T) {
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var fpgaBitStreamDir = "testdata/intel.com/fpga"
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tcases := []struct {
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name string
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bitstreamDir string
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region string
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afu string
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expectedErr bool
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}{
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{
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name: "Correct OPAE bitstream file",
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bitstreamDir: fpgaBitStreamDir,
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region: "69528db6eb31577a8c3668f9faa081f6",
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afu: "d8424dc4a4a3c413f89e433683f9040b",
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expectedErr: false,
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},
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{
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name: "Get broken OPAE bistream file",
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bitstreamDir: fpgaBitStreamDir,
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18",
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expectedErr: true,
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},
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{
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name: "Get broken OpenCL bistream file",
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bitstreamDir: fpgaBitStreamDir,
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region: "ce48969398f05f33946d560708be108a",
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afu: "d7724dc4a4a3c413f89e433683f9040b",
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expectedErr: true,
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},
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{
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name: "Bitstream not found",
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bitstreamDir: fpgaBitStreamDir,
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region: "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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afu: "yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy",
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expectedErr: true,
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},
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}
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for _, tc := range tcases {
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t.Run(tc.name, func(t *testing.T) {
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_, err := GetFPGABitstream(tc.bitstreamDir, tc.region, tc.afu)
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if err != nil {
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if !tc.expectedErr {
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t.Errorf("unexpected error occurred: %+v", err)
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}
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return
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}
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})
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}
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}
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func TestOpen(t *testing.T) {
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tcases := []struct {
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name string
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fname string
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expectedError bool
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}{
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{
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name: "correct GBS",
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fname: "testdata/intel.com/fpga/69528db6eb31577a8c3668f9faa081f6/d8424dc4a4a3c413f89e433683f9040b.gbs",
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},
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{
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name: "Unsupported file format",
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fname: "test.unsupported",
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expectedError: true,
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},
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}
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for _, tc := range tcases {
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t.Run(tc.name, func(t *testing.T) {
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_, err := Open(tc.fname)
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if tc.expectedError && err == nil {
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t.Error("unexpected success")
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}
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if !tc.expectedError && err != nil {
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t.Errorf("unexpected error: %+v", err)
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}
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})
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}
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}
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