mirror of
https://github.com/intel/intel-device-plugins-for-kubernetes.git
synced 2025-06-03 03:59:37 +00:00
71d08224ee
Move all the fpga components to using klog for logging
and debug. This includes replacing our homebrew 'fatal()'
with klog.Error().
Modify the deployment files to move from `-debug` to
`-v`, and set their default level to '1' (Info), rather
than full debug mode ('4').
Signed-off-by: Graham Whaley <graham.whaley@intel.com>
422 lines
11 KiB
Go
422 lines
11 KiB
Go
// Copyright 2018 Intel Corporation. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package main
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import (
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"flag"
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"testing"
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corev1 "k8s.io/api/core/v1"
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"k8s.io/apimachinery/pkg/api/resource"
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metav1 "k8s.io/apimachinery/pkg/apis/meta/v1"
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"k8s.io/klog"
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fpgav1 "github.com/intel/intel-device-plugins-for-kubernetes/pkg/apis/fpga.intel.com/v1"
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)
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func init() {
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flag.Set("v", "4")
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}
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func TestPatcherStorageFunctions(t *testing.T) {
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af := &fpgav1.AcceleratorFunction{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10-nlb0",
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},
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Spec: fpgav1.AcceleratorFunctionSpec{
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AfuID: "d8424dc4a4a3c413f89e433683f9040b",
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},
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}
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region := &fpgav1.FpgaRegion{
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ObjectMeta: metav1.ObjectMeta{
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Name: "arria10",
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},
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Spec: fpgav1.FpgaRegionSpec{
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InterfaceID: "ce48969398f05f33946d560708be108a",
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},
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}
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p, err := newPatcher(preprogrammed)
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if err != nil {
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t.Fatal(err)
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}
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p.addAf(af)
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if len(p.afMap) != 1 || len(p.resourceMap) != 1 {
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t.Error("Failed to add AF to patcher")
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}
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p.removeAf(af.Name)
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if len(p.afMap) != 0 || len(p.resourceMap) != 0 {
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t.Error("Failed to remove AF from patcher")
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}
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p.addRegion(region)
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if len(p.regionMap) != 1 || len(p.resourceMap) != 1 {
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t.Error("Failed to add fpga region to patcher")
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}
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p.removeRegion(region.Name)
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if len(p.regionMap) != 0 || len(p.resourceMap) != 0 {
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t.Error("Failed to remove fpga region from patcher")
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}
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}
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func TestGetPatchOpsPreprogrammed(t *testing.T) {
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tcases := []struct {
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name string
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resourceMap map[string]string
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container corev1.Container
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expectedErr bool
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expectedOps int
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}{
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{
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name: "Empty container",
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},
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{
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name: "Unknown resource in limits",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-unknown": resource.MustParse("1"),
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"cpu": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unknown resource in requests",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-unknown": resource.MustParse("1"),
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"cpu": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Successful case",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"cpu": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"cpu": resource.MustParse("1"),
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},
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},
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},
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resourceMap: map[string]string{
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"fpga.intel.com/arria10-nlb0": rfc6901Escaper.Replace("fpga.intel.com/af-d8424dc4a4a3c413f89e433683f9040b"),
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},
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expectedOps: 2,
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},
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}
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for _, tt := range tcases {
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p := &patcher{
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resourceMap: tt.resourceMap,
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}
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ops, err := p.getPatchOpsPreprogrammed(0, tt.container)
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if tt.expectedErr && err == nil {
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t.Errorf("Test case '%s': no error returned", tt.name)
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}
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if !tt.expectedErr && err != nil {
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t.Errorf("Test case '%s': unexpected error %v", tt.name, err)
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}
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if len(ops) != tt.expectedOps {
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t.Errorf("test case '%s': expected %d ops, but got %d\n%v", tt.name, tt.expectedOps, len(ops), ops)
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}
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}
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}
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func TestParseResourceName(t *testing.T) {
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tcases := []struct {
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input string
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interfaceID string
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afuID string
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afMap map[string]string
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regionMap map[string]string
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expectedErr bool
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}{
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{
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input: "fpga.intel.com/arria10",
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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interfaceID: "ce48969398f05f33946d560708be108a",
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},
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{
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input: "fpga.intel.com/arria10-unknown",
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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expectedErr: true,
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},
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{
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input: "fpga.intel.com/unknown",
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expectedErr: true,
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},
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{
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input: "fpga.example.com/something",
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},
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{
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input: "fpga.intel.com/arria10-nlb0",
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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afMap: map[string]string{
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"arria10-nlb0": "d8424dc4a4a3c413f89e433683f9040b",
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},
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interfaceID: "ce48969398f05f33946d560708be108a",
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afuID: "d8424dc4a4a3c413f89e433683f9040b",
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},
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}
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for num, tt := range tcases {
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p := &patcher{
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afMap: tt.afMap,
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regionMap: tt.regionMap,
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}
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interfaceID, afuID, err := p.parseResourceName(tt.input)
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if tt.expectedErr {
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if err != nil {
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continue
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} else {
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t.Errorf("In case %d we didn't get error", num)
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}
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}
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if tt.interfaceID != interfaceID || tt.afuID != afuID {
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t.Errorf("In case %d expected (%s, %s), but got (%s, %s)", num, tt.interfaceID, tt.afuID, interfaceID, afuID)
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}
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}
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}
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func TestGetPatchOpsOrchestrated(t *testing.T) {
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tcases := []struct {
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name string
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container corev1.Container
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afMap map[string]string
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regionMap map[string]string
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expectedErr bool
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expectedOps int
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}{
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{
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name: "Successful handling",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"cpu": resource.MustParse("1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"cpu": resource.MustParse("1"),
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},
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},
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Env: []corev1.EnvVar{
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{
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Name: "SOME_VAR",
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Value: "fake value",
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},
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},
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},
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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afMap: map[string]string{
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"arria10-nlb0": "d8424dc4a4a3c413f89e433683f9040b",
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},
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expectedOps: 5,
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},
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{
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name: "Unequal FPGA resources in Limits and Requests 1",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb3": resource.MustParse("2"),
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},
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},
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},
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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afMap: map[string]string{
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"arria10-nlb0": "d8424dc4a4a3c413f89e433683f9040b",
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"arria10-nlb3": "f7df405cbd7acf7222f144b0b93acd18",
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},
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expectedErr: true,
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},
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{
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name: "Unequal FPGA resources in Limits and Requests 2",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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"fpga.intel.com/arria10-nlb3": resource.MustParse("1"),
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},
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},
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},
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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afMap: map[string]string{
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"arria10-nlb0": "d8424dc4a4a3c413f89e433683f9040b",
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"arria10-nlb3": "f7df405cbd7acf7222f144b0b93acd18",
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},
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expectedErr: true,
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},
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{
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name: "Unknown FPGA model in Requests",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Requests: corev1.ResourceList{
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"fpga.intel.com/unknown-nlb0": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unknown AFU in Requests",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-unknown": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unknown FPGA model in Limits",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/unknown-nlb0": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Unknown AFU in Limits",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-unknown": resource.MustParse("1"),
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},
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},
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},
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expectedErr: true,
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},
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{
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name: "Wrong ENV",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1"),
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},
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},
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Env: []corev1.EnvVar{
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{
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Name: "FPGA_REGION",
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Value: "fake value",
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},
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},
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},
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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afMap: map[string]string{
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"arria10-nlb0": "d8424dc4a4a3c413f89e433683f9040b",
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},
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expectedErr: true,
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},
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{
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name: "Wrong type of quantity",
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container: corev1.Container{
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Resources: corev1.ResourceRequirements{
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Limits: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1.1"),
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},
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Requests: corev1.ResourceList{
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"fpga.intel.com/arria10-nlb0": resource.MustParse("1.1"),
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},
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},
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},
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regionMap: map[string]string{
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"arria10": "ce48969398f05f33946d560708be108a",
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},
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afMap: map[string]string{
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"arria10-nlb0": "d8424dc4a4a3c413f89e433683f9040b",
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},
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expectedErr: true,
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},
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}
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for _, tt := range tcases {
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p := &patcher{
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afMap: tt.afMap,
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regionMap: tt.regionMap,
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}
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klog.V(4).Info(tt.name)
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ops, err := p.getPatchOpsOrchestrated(0, tt.container)
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if tt.expectedErr && err == nil {
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t.Errorf("Test case '%s': no error returned", tt.name)
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}
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if !tt.expectedErr && err != nil {
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t.Errorf("Test case '%s': unexpected error %+v", tt.name, err)
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}
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if len(ops) != tt.expectedOps {
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t.Errorf("test case '%s': expected %d ops, but got %d\n%v", tt.name, tt.expectedOps, len(ops), ops)
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}
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}
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}
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func TestNewPatcherManager(t *testing.T) {
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tcases := []struct {
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name string
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defaultMode string
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expectedErr bool
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}{
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{
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name: "Everything is OK",
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defaultMode: preprogrammed,
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},
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{
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name: "Unknown default mode",
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defaultMode: "unknownMode",
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expectedErr: true,
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},
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}
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for _, tt := range tcases {
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t.Run(tt.name, func(t *testing.T) {
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_, err := newPatcherManager(tt.defaultMode)
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if tt.expectedErr && err == nil {
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t.Errorf("Test case '%s': no error returned", tt.name)
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}
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if !tt.expectedErr && err != nil {
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t.Errorf("Test case '%s': unexpected error %+v", tt.name, err)
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}
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})
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}
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}
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