mirror of
https://github.com/intel/intel-device-plugins-for-kubernetes.git
synced 2025-06-03 03:59:37 +00:00
79a0928646
intel-fpga-initcontainer installs OPAE and OpenCL tools into /opt/intel/fpga-sw directory. Used fpgaconf-wrapper, aocl-wrapper and packager tools by CRI hook to program OPAE and OpenCL bitstreams. Added support for OpenCL bitstreams: the hook tries to find either OPAE or OpenCL bitstream suitable for requested region and AFU and programs it using OPAE or OpenCL tools. Fixes #71
554 lines
17 KiB
Go
554 lines
17 KiB
Go
// Copyright 2018 Intel Corporation. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package main
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import (
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"io/ioutil"
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"os"
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"path"
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"testing"
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"k8s.io/utils/exec"
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fakeexec "k8s.io/utils/exec/testing"
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"github.com/intel/intel-device-plugins-for-kubernetes/pkg/debug"
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)
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func init() {
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debug.Activate()
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}
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func TestGetFPGAParams(t *testing.T) {
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tcases := []struct {
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stdinJSON string
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configJSON string
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afuIDPath string
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expectedErr bool
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expectedRegion string
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expectedAFU string
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expectedDeviceNum string
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}{
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-correct.json",
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expectedErr: false,
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expectedRegion: "ce48969398f05f33946d560708be108a",
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expectedAFU: "f7df405cbd7acf7222f144b0b93acd18",
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expectedDeviceNum: "0",
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},
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{
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stdinJSON: "stdin-no-bundle.json",
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configJSON: "config-correct.json",
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expectedErr: true,
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},
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{
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stdinJSON: "stdin-bundle-dir-doesnt-exist.json",
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configJSON: "config-correct.json",
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expectedErr: true,
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-broken-json.json",
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expectedErr: true,
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-process.json",
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expectedErr: true,
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-env.json",
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expectedErr: true,
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-region.json",
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expectedErr: true,
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-afu.json",
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expectedErr: true,
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expectedRegion: "ce48969398f05f33946d560708be108a",
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-linux.json",
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expectedErr: true,
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expectedRegion: "ce48969398f05f33946d560708be108a",
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expectedAFU: "f7df405cbd7acf7222f144b0b93acd18",
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-devices.json",
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expectedErr: true,
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expectedRegion: "ce48969398f05f33946d560708be108a",
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expectedAFU: "f7df405cbd7acf7222f144b0b93acd18",
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},
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{
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stdinJSON: "stdin-correct.json",
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configJSON: "config-no-FPGA-devices.json",
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expectedErr: true,
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expectedRegion: "ce48969398f05f33946d560708be108a",
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expectedAFU: "f7df405cbd7acf7222f144b0b93acd18",
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},
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}
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for _, tc := range tcases {
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stdin, err := os.Open(path.Join("testdata", tc.stdinJSON))
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if err != nil {
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t.Fatalf("can't open file %s: %v", tc.stdinJSON, err)
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}
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content, err := decodeJSONStream(stdin)
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if err != nil {
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t.Fatalf("can't decode json file %s: %+v", tc.stdinJSON, err)
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}
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he := newHookEnv("", tc.configJSON, nil, "")
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params, err := he.getFPGAParams(content)
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if err != nil {
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if !tc.expectedErr {
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t.Errorf("unexpected error: %+v", err)
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}
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} else {
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if params.region != tc.expectedRegion {
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t.Errorf("expected region: %s, actual: %s", tc.expectedRegion, params.region)
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} else if params.afu != tc.expectedAFU {
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t.Errorf("expected AFU: %s, actual: %s", tc.expectedAFU, params.afu)
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} else if params.devNum != tc.expectedDeviceNum {
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t.Errorf("expected device number: %s, actual: %s", tc.expectedDeviceNum, params.devNum)
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}
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}
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}
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}
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func genFakeActions(fcmd *fakeexec.FakeCmd, num int) []fakeexec.FakeCommandAction {
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var actions []fakeexec.FakeCommandAction
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for i := 0; i < num; i++ {
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actions = append(actions, func(cmd string, args ...string) exec.Cmd {
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return fakeexec.InitFakeCmd(fcmd, cmd, args...)
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})
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}
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return actions
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}
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func TestValidate(t *testing.T) {
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var fpgaBitStreamDir = "testdata/intel.com/fpga"
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tcases := []struct {
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params *fpgaParams
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expectedErr bool
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fakeAction []fakeexec.FakeCombinedOutputAction
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}{
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: false,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-correct.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "d7724dc4a4a3c413f89e433683f9040b"},
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expectedErr: false,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return nil, nil
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) { return nil, &fakeexec.FakeExitError{Status: 1} },
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-broken-json.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-no-afu-image.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-no-interface-uuid.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-no-accelerator-clusters.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05fxxxxxxxxxxxxxxxxxx",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-correct.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-no-accelerator-type-uuid.json")
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},
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},
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},
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{
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params: &fpgaParams{
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region: "ce48969398f05f33946d560708be108a",
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afu: "d8424dc4a4a3c413f89e433683f9040b"},
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expectedErr: true,
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fakeAction: []fakeexec.FakeCombinedOutputAction{
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func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-correct.json")
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},
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},
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},
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}
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for _, tc := range tcases {
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fcmd := fakeexec.FakeCmd{CombinedOutputScript: tc.fakeAction}
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execer := fakeexec.FakeExec{CommandScript: genFakeActions(&fcmd, len(fcmd.CombinedOutputScript))}
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he := newHookEnv(fpgaBitStreamDir, "", &execer, "")
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bitStream, err := he.getBitStream(tc.params)
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if err != nil && !tc.expectedErr {
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t.Errorf("unexpected error: unable to get bitstream: %+v", err)
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continue
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}
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err = bitStream.validate()
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if err != nil && !tc.expectedErr {
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t.Errorf("unexpected error: bitstream validation failed: %+v", err)
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}
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}
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}
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func genFpgaConfAction(he *hookEnv, afuIDTemplate string, returnError bool) fakeexec.FakeCombinedOutputAction {
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return func() ([]byte, error) {
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if returnError {
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return []byte("error"), &fakeexec.FakeExitError{Status: 1}
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}
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he.afuIDTemplate = afuIDTemplate // emulate reprogramming
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return []byte(""), nil
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}
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}
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func TestProgram(t *testing.T) {
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var fpgaBitStreamDir = "testdata/intel.com/fpga"
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tcases := []struct {
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params *fpgaParams
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afuIDTemplate string
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newAFUIDTemplate string
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expectedErr bool
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fpgaconfErr bool
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}{
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
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newAFUIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_f7df405cbd7acf7222f144b0b93acd18",
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "d7724dc4a4a3c413f89e433683f9040b"},
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afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
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newAFUIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d7724dc4a4a3c413f89e433683f9040b",
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7dfaaacbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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expectedErr: true,
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fpgaconfErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "18b7bffa2eb54aa096ef4230dafacb5a"},
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expectedErr: true,
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fpgaconfErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "d8424dc4a4a3c413f89e433683f9040b"},
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afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/doesnt_exist",
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expectedErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "d8424dc4a4a3c413f89e433683f9040b"},
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afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_f7df405cbd7acf7222f144b0b93acd18",
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newAFUIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_f7df405cbd7acf7222f144b0b93acd18",
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expectedErr: true,
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},
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}
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for _, tc := range tcases {
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he := newHookEnv(fpgaBitStreamDir, "", nil, tc.afuIDTemplate)
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actions := []fakeexec.FakeCombinedOutputAction{genFpgaConfAction(he, tc.newAFUIDTemplate, tc.fpgaconfErr)}
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fcmd := fakeexec.FakeCmd{CombinedOutputScript: actions}
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he.execer = &fakeexec.FakeExec{CommandScript: genFakeActions(&fcmd, len(fcmd.CombinedOutputScript))}
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bitStream, err := he.getBitStream(tc.params)
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if err != nil {
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if !tc.expectedErr {
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t.Errorf("unexpected error: unable to get bitstream: %+v", err)
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}
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continue
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}
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err = bitStream.program()
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if err != nil && !tc.expectedErr {
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t.Errorf("unexpected error: programming bitstream failed: %+v", err)
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}
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}
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}
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func TestProcess(t *testing.T) {
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tcases := []struct {
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stdinJSON string
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configJSON string
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params *fpgaParams
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afuIDTemplate string
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newAFUIDTemplate string
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expectedErr bool
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fpgaconfErr bool
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gbsInfoAction fakeexec.FakeCombinedOutputAction
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}{
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "d8424dc4a4a3c413f89e433683f9040b"},
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stdinJSON: "stdin-correct.json",
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configJSON: "config-correct.json",
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afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_f7df405cbd7acf7222f144b0b93acd18",
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gbsInfoAction: func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-correct.json")
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},
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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stdinJSON: "stdin-correct.json",
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configJSON: "config-correct.json",
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afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
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newAFUIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_f7df405cbd7acf7222f144b0b93acd18",
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gbsInfoAction: func() ([]byte, error) {
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return ioutil.ReadFile("testdata/gbs-info-correct.json")
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},
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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stdinJSON: "stdin-broken-json.json",
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expectedErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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stdinJSON: "stdin-no-annotations.json",
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expectedErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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stdinJSON: "stdin-no-intel-annotation.json",
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expectedErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
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region: "ce48969398f05f33946d560708be108a",
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afu: "f7df405cbd7acf7222f144b0b93acd18"},
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stdinJSON: "stdin-incorrect-intel-annotation.json",
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expectedErr: true,
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},
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{
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params: &fpgaParams{
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devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "f7df405cbd7acf7222f144b0b93acd18"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-no-afu.json",
|
|
afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
expectedErr: true,
|
|
},
|
|
{
|
|
params: &fpgaParams{
|
|
devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "f7df405cbd7acf7222f144b0b93acd18"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-correct.json",
|
|
expectedErr: true,
|
|
},
|
|
{
|
|
params: &fpgaParams{
|
|
devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "f7df405cbd7acf7222f144b0b93acd18"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-non-existing-bitstream.json",
|
|
afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
expectedErr: true,
|
|
},
|
|
{
|
|
params: &fpgaParams{
|
|
devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "f7df405cbd7acf7222f144b0b93acd18"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-correct.json",
|
|
afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
expectedErr: true,
|
|
gbsInfoAction: func() ([]byte, error) {
|
|
return ioutil.ReadFile("testdata/gbs-info-no-accelerator-type-uuid.json")
|
|
},
|
|
},
|
|
{
|
|
params: &fpgaParams{
|
|
devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "d8424dc4a4a3c413f89e433683f9040b"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-correct.json",
|
|
afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
expectedErr: true,
|
|
gbsInfoAction: func() ([]byte, error) {
|
|
return ioutil.ReadFile("testdata/gbs-info-correct.json")
|
|
},
|
|
},
|
|
{
|
|
params: &fpgaParams{
|
|
devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "d8424dc4a4a3c413f89e433683f9040b"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-correct.json",
|
|
afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
expectedErr: true,
|
|
fpgaconfErr: true,
|
|
gbsInfoAction: func() ([]byte, error) {
|
|
return ioutil.ReadFile("testdata/gbs-info-correct.json")
|
|
},
|
|
},
|
|
{
|
|
params: &fpgaParams{
|
|
devNum: "0",
|
|
region: "ce48969398f05f33946d560708be108a",
|
|
afu: "f7df405cbd7acf7222f144b0b93acd18"},
|
|
stdinJSON: "stdin-correct.json",
|
|
configJSON: "config-correct.json",
|
|
afuIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
newAFUIDTemplate: "testdata/sys/class/fpga/intel-fpga-dev.%s/intel-fpga-port.%s/afu_id_d8424dc4a4a3c413f89e433683f9040b",
|
|
expectedErr: true,
|
|
gbsInfoAction: func() ([]byte, error) {
|
|
return ioutil.ReadFile("testdata/gbs-info-correct.json")
|
|
},
|
|
},
|
|
}
|
|
|
|
for _, tc := range tcases {
|
|
stdin, err := os.Open(path.Join("testdata", tc.stdinJSON))
|
|
if err != nil {
|
|
t.Fatalf("can't open file %s: %v", tc.stdinJSON, err)
|
|
}
|
|
|
|
he := newHookEnv("testdata/intel.com/fpga", tc.configJSON, nil, tc.afuIDTemplate)
|
|
|
|
actions := []fakeexec.FakeCombinedOutputAction{
|
|
tc.gbsInfoAction,
|
|
genFpgaConfAction(he, tc.newAFUIDTemplate, tc.fpgaconfErr),
|
|
}
|
|
fcmd := fakeexec.FakeCmd{CombinedOutputScript: actions}
|
|
he.execer = &fakeexec.FakeExec{CommandScript: genFakeActions(&fcmd, len(fcmd.CombinedOutputScript))}
|
|
|
|
err = he.process(stdin)
|
|
|
|
if err != nil && !tc.expectedErr {
|
|
t.Errorf("unexpected error: %+v", err)
|
|
}
|
|
}
|
|
}
|