mirror of
https://github.com/intel/intel-device-plugins-for-kubernetes.git
synced 2025-06-03 03:59:37 +00:00
c60a3afb26
golangci-lint version < v1.53.0 used nakedret linter that did not check return values in conditionals. That got changed in v1.53.0 and some of our code starts failing because of naked returns from conditionals. Update the code to get nakedret linter passing. Signed-off-by: Hyeongju Johannes Lee <hyeongju.lee@intel.com>
424 lines
10 KiB
Go
424 lines
10 KiB
Go
// Copyright 2019 Intel Corporation. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package main
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import (
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"flag"
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"fmt"
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"io"
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"log"
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"os"
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"path/filepath"
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"github.com/pkg/errors"
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"github.com/intel/intel-device-plugins-for-kubernetes/pkg/fpga"
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"github.com/intel/intel-device-plugins-for-kubernetes/pkg/fpga/bitstream"
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)
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const (
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fpgaBitStreamDirectory = "/srv/intel.com/fpga"
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)
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func main() {
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var (
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err error
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bitstream, device string
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dryRun, force, quiet bool
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port uint
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)
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flag.StringVar(&bitstream, "b", "", "Path to bitstream file (GBS or AOCX)")
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flag.StringVar(&device, "d", "", "Path to device node (FME or Port)")
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flag.BoolVar(&dryRun, "dry-run", false, "Don't write/program, just validate and log")
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flag.BoolVar(&force, "force", false, "Force overwrite operation for installing bitstreams")
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flag.BoolVar(&quiet, "q", false, "Quiet mode. Only errors will be reported")
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flag.UintVar(&port, "p", 0, "Port number for release/assign operations. Default: 0")
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flag.Parse()
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if flag.NArg() < 1 {
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log.Fatal("Please provide command: info, fpgainfo, install, list, fmeinfo, portinfo, list-fme, list-port, pr, release, assign")
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}
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cmd := flag.Arg(0)
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err = validateFlags(cmd, bitstream, device, port)
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if err != nil {
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log.Fatalf("Invalid arguments: %+v", err)
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}
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switch cmd {
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case "info":
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err = printBitstreamInfo(bitstream, quiet)
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case "pr":
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err = doPR(device, bitstream, dryRun, quiet)
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case "fpgainfo", "fmeinfo", "portinfo":
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// Inefficient code, but making gocyclo happy...
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err = fpgaInfo(device, quiet)
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case "install":
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err = installBitstream(bitstream, dryRun, force, quiet)
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case "list":
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err = listDevices(true, true, quiet)
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case "list-fme":
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err = listDevices(true, false, quiet)
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case "list-port":
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err = listDevices(false, true, quiet)
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case "release":
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err = portReleaseOrAssign(device, port, true, quiet)
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case "assign":
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err = portReleaseOrAssign(device, port, false, quiet)
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default:
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err = errors.Errorf("unknown command %+v", flag.Args())
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}
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if err != nil {
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log.Fatalf("%+v", err)
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}
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}
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func validateFlags(cmd, bitstream, device string, port uint) error {
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switch cmd {
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case "info", "install":
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// bitstream must not be empty
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if bitstream == "" {
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return errors.Errorf("bitstream filename is missing")
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}
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case "fpgainfo", "fmeinfo", "portinfo", "release", "assign":
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// device must not be empty
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if device == "" {
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return errors.Errorf("FPGA device name is missing")
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}
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case "pr":
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// device and bitstream can't be empty
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if bitstream == "" {
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return errors.Errorf("bitstream filename is missing")
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}
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if device == "" {
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return errors.Errorf("FPGA device name is missing")
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}
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}
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return nil
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}
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func installBitstream(fname string, dryRun, force, quiet bool) (err error) {
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info, err := bitstream.Open(fname)
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if err != nil {
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return err
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}
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defer info.Close()
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installPath := info.InstallPath(fpgaBitStreamDirectory)
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if !quiet {
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fmt.Printf("Installing bitstream %q as %q\n", fname, installPath)
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if dryRun {
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fmt.Println("Dry-run: no copying performed")
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return nil
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}
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}
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err = os.MkdirAll(filepath.Dir(installPath), 0755)
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if err != nil {
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return errors.Wrap(err, "unable to create destination directory")
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}
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src, err := os.Open(fname)
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if err != nil {
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return errors.Wrap(err, "can't open bitstream file")
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}
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defer src.Close()
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flags := os.O_WRONLY | os.O_CREATE | os.O_TRUNC
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if !force {
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flags = flags | os.O_EXCL
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}
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dst, err := os.OpenFile(installPath, flags, 0644)
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if err != nil {
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if os.IsExist(err) {
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return errors.Wrapf(err, "destination file %q already exist. Use --force to overwrite it", installPath)
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}
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return errors.Wrap(err, "can't create destination file")
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}
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defer dst.Close()
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_, err = io.Copy(dst, src)
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return err
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}
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func printBitstreamInfo(fname string, quiet bool) (err error) {
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info, err := bitstream.Open(fname)
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if err != nil {
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return
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}
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defer info.Close()
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fmt.Printf("Bitstream file : %q\n", fname)
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fmt.Printf("Interface UUID : %q\n", info.InterfaceUUID())
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fmt.Printf("Accelerator Type UUID : %q\n", info.AcceleratorTypeUUID())
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fmt.Printf("Unique UUID : %q\n", info.UniqueUUID())
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fmt.Printf("Installation Path : %q\n", info.InstallPath(fpgaBitStreamDirectory))
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extra := info.ExtraMetadata()
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if len(extra) > 0 && !quiet {
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fmt.Println("Extra:")
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for k, v := range extra {
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fmt.Printf("\t%s : %q\n", k, v)
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}
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}
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return
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}
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func fpgaInfo(fname string, quiet bool) error {
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switch {
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case fpga.IsFpgaFME(fname):
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return fmeInfo(fname, quiet)
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case fpga.IsFpgaPort(fname):
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return portInfo(fname, quiet)
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}
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return errors.Errorf("unknown FPGA device file %s", fname)
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}
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func fmeInfo(fname string, quiet bool) error {
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fme, err := fpga.NewFME(fname)
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if err != nil {
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return err
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}
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defer fme.Close()
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// check that kernel API is compatible
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if _, err := fme.GetAPIVersion(); err != nil {
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return errors.Wrap(err, "kernel API mismatch")
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}
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return printFpgaFME(fme, quiet)
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}
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func printFpgaFME(f fpga.FME, quiet bool) (err error) {
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fmt.Println("//****** FME ******//")
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fmt.Printf("Name : %s\n", f.GetName())
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fmt.Printf("Device Node : %s\n", f.GetDevPath())
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fmt.Printf("SysFS Path : %s\n", f.GetSysFsPath())
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pci, err := f.GetPCIDevice()
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if err != nil {
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return
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}
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printPCIeInfo(pci, quiet)
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fmt.Printf("Interface UUID : %s\n", f.GetInterfaceUUID())
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if !quiet {
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if apiVer, err := f.GetAPIVersion(); err == nil {
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fmt.Printf("Kernet API Version : %d\n", apiVer)
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}
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fmt.Printf("Ports Num : %d\n", f.GetPortsNum())
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if id, err := f.GetSocketID(); err == nil {
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fmt.Printf("Socket Id : %d\n", id)
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}
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fmt.Printf("Bitstream Id : %s\n", f.GetBitstreamID())
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fmt.Printf("Bitstream Metadata : %s\n", f.GetBitstreamMetadata())
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}
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return
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}
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func portReleaseOrAssign(fname string, port uint, release, quiet bool) error {
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fme, err := fpga.NewFME(fname)
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if err != nil {
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return err
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}
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defer fme.Close()
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// check that kernel API is compatible
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if _, err := fme.GetAPIVersion(); err != nil {
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return errors.Wrap(err, "kernel API mismatch")
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}
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if release {
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return fme.PortRelease(uint32(port))
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}
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return fme.PortAssign(uint32(port))
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}
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func portInfo(fname string, quiet bool) error {
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port, err := fpga.NewPort(fname)
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if err != nil {
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return err
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}
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defer port.Close()
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// check that kernel API is compatible
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if _, err = port.GetAPIVersion(); err != nil {
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return errors.Wrap(err, "kernel API mismatch")
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}
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return printFpgaPort(port, quiet)
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}
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func printFpgaPort(f fpga.Port, quiet bool) (err error) {
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fmt.Println("//****** PORT ******//")
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fmt.Printf("Name : %s\n", f.GetName())
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fmt.Printf("Device Node : %s\n", f.GetDevPath())
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fmt.Printf("SysFS Path : %s\n", f.GetSysFsPath())
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pci, err := f.GetPCIDevice()
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if err != nil {
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return err
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}
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printPCIeInfo(pci, quiet)
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fme, err := f.GetFME()
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if err != nil {
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return err
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}
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fmt.Printf("FME Name : %s\n", fme.GetName())
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num, err := f.GetPortID()
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if err != nil {
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return err
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}
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fmt.Printf("Port Id : %d\n", num)
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fmt.Printf("Interface UUID : %s\n", f.GetInterfaceUUID())
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fmt.Printf("Accelerator UUID : %s\n", f.GetAcceleratorTypeUUID())
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if quiet {
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return err
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}
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apiVer, err := f.GetAPIVersion()
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if err != nil {
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return err
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}
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fmt.Printf("Kernet API Version : %d\n", apiVer)
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pi, err := f.PortGetInfo()
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if err != nil {
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return err
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}
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fmt.Printf("Port Regions : %d\n", pi.Regions)
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for idx := uint32(0); idx < pi.Regions; idx++ {
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ri, err := f.PortGetRegionInfo(idx)
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if err != nil {
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return err
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}
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fmt.Printf("Port Region (Index/Size/Offset) : %d / %d / %d\n", ri.Index, ri.Size, ri.Offset)
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}
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return nil
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}
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func printPCIeInfo(pci *fpga.PCIDevice, quiet bool) {
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fmt.Printf("PCIe s:b:d:f : %s\n", pci.BDF)
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if pci.PhysFn != nil && !quiet {
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fmt.Printf("Physical Function PCIe s:b:d:f : %s\n", pci.PhysFn.BDF)
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}
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fmt.Printf("Device Id : %s:%s\n", pci.Vendor, pci.Device)
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if !quiet {
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fmt.Printf("Device Class : %s\n", pci.Class)
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fmt.Printf("Local CPUs : %s\n", pci.CPUs)
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fmt.Printf("NUMA : %s\n", pci.NUMA)
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if pci.VFs != "" {
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fmt.Printf("SR-IOV Virtual Functions : %s\n", pci.VFs)
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}
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if pci.TotalVFs != "" {
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fmt.Printf("SR-IOV maximum Virtual Functions : %s\n", pci.TotalVFs)
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}
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}
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}
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func doPR(dev, fname string, dryRun, quiet bool) error {
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port, err := fpga.NewPort(dev)
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if err != nil {
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return err
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}
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defer port.Close()
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// check that kernel API is compatible
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if _, err = port.GetAPIVersion(); err != nil {
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return errors.Wrap(err, "kernel API mismatch")
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}
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bs, err := bitstream.Open(fname)
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if err != nil {
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return err
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}
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defer bs.Close()
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if !quiet {
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fmt.Printf("Before: Interface ID: %q AFU ID: %q\n", port.GetInterfaceUUID(), port.GetAcceleratorTypeUUID())
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fmt.Printf("Programming %q to port %q: ", fname, dev)
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}
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err = port.PR(bs, dryRun)
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if !quiet {
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if err != nil {
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fmt.Println("FAILED")
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} else {
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fmt.Println("OK")
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}
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fmt.Printf("After : Interface ID: %q AFU ID: %q\n", port.GetInterfaceUUID(), port.GetAcceleratorTypeUUID())
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}
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return err
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}
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func listDevices(listFMEs, listPorts, quiet bool) error {
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fmes, ports := fpga.ListFpgaDevices()
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if listFMEs {
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if !quiet {
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fmt.Printf("Detected FPGA FMEs: %d\n", len(fmes))
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}
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for _, v := range fmes {
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fmt.Println(v)
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}
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}
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if listPorts {
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if !quiet {
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fmt.Printf("Detected FPGA Ports: %d\n", len(ports))
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}
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for _, v := range ports {
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fmt.Println(v)
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}
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}
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return nil
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}
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