mirror of
https://github.com/intel/intel-device-plugins-for-kubernetes.git
synced 2025-06-03 03:59:37 +00:00
c60a3afb26
golangci-lint version < v1.53.0 used nakedret linter that did not check return values in conditionals. That got changed in v1.53.0 and some of our code starts failing because of naked returns from conditionals. Update the code to get nakedret linter passing. Signed-off-by: Hyeongju Johannes Lee <hyeongju.lee@intel.com>
492 lines
12 KiB
Go
492 lines
12 KiB
Go
// Copyright 2019 Intel Corporation. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package fpga
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import (
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"math"
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"path/filepath"
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"strconv"
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"unsafe"
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"github.com/intel/intel-device-plugins-for-kubernetes/pkg/fpga/bitstream"
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"github.com/pkg/errors"
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)
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const (
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intelFpgaFmePrefix = "intel-fpga-fme."
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intelFpgaPortPrefix = "intel-fpga-port."
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intelFpgaFmeGlobPCI = "fpga/intel-fpga-dev.*/intel-fpga-fme.*"
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)
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// IntelFpgaFME represent Intel FPGA FME device.
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type IntelFpgaFME struct {
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FME
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DevPath string
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SysFsPath string
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Name string
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PCIDevice *PCIDevice
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SocketID string
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Dev string
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CompatID string
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BitstreamID string
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BitstreamMetadata string
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PortsNum string
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}
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// Close closes open device.
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func (f *IntelFpgaFME) Close() error {
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return nil
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}
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// NewIntelFpgaFME Opens device.
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func NewIntelFpgaFME(dev string) (FME, error) {
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fme := &IntelFpgaFME{DevPath: dev}
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if err := checkPCIDeviceType(fme); err != nil {
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return nil, err
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}
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if err := fme.updateProperties(); err != nil {
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return nil, err
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}
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return fme, nil
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}
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// IntelFpgaPort represent IntelFpga FPGA Port device.
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type IntelFpgaPort struct {
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Port
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FME FME
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DevPath string
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SysFsPath string
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Name string
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PCIDevice *PCIDevice
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Dev string
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AFUID string
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ID string
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}
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// Close closes open device.
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func (f *IntelFpgaPort) Close() error {
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if f.FME != nil {
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defer f.FME.Close()
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}
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return nil
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}
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// NewIntelFpgaPort Opens device.
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func NewIntelFpgaPort(dev string) (Port, error) {
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port := &IntelFpgaPort{DevPath: dev}
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if err := checkPCIDeviceType(port); err != nil {
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port.Close()
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return nil, err
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}
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if err := port.updateProperties(); err != nil {
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port.Close()
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return nil, err
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}
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return port, nil
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}
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// common ioctls for FME and Port.
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func commonIntelFpgaGetAPIVersion(fd string) (int, error) {
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v, err := ioctlDev(fd, FPGA_GET_API_VERSION, 0)
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return int(v), err
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}
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func commonIntelFpgaCheckExtension(fd string) (int, error) {
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v, err := ioctlDev(fd, FPGA_CHECK_EXTENSION, 0)
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return int(v), err
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}
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// GetAPIVersion Report the version of the driver API.
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// * Return: Driver API Version.
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func (f *IntelFpgaFME) GetAPIVersion() (int, error) {
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return commonIntelFpgaGetAPIVersion(f.DevPath)
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}
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// CheckExtension Check whether an extension is supported.
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// * Return: 0 if not supported, otherwise the extension is supported.
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func (f *IntelFpgaFME) CheckExtension() (int, error) {
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return commonIntelFpgaCheckExtension(f.DevPath)
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}
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// GetAPIVersion Report the version of the driver API.
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// * Return: Driver API Version.
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func (f *IntelFpgaPort) GetAPIVersion() (int, error) {
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return commonIntelFpgaGetAPIVersion(f.DevPath)
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}
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// CheckExtension Check whether an extension is supported.
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// * Return: 0 if not supported, otherwise the extension is supported.
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func (f *IntelFpgaPort) CheckExtension() (int, error) {
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return commonIntelFpgaCheckExtension(f.DevPath)
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}
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// FME interfaces
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// PortPR does Partial Reconfiguration based on Port ID and Buffer (Image)
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// provided by caller.
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// - Return: 0 on success, -errno on failure.
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// - If IntelFpga_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
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// some errors during PR, under this case, the user can fetch HW error info
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// from the status of FME's fpga manager.
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func (f *IntelFpgaFME) PortPR(port uint32, bitstream []byte) error {
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var value IntelFpgaFmePortPR
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value.Argsz = uint32(unsafe.Sizeof(value))
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value.Port_id = port
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value.Buffer_size = uint32(len(bitstream))
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value.Buffer_address = uint64(uintptr(unsafe.Pointer(&bitstream[0])))
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_, err := ioctlDev(f.DevPath, FPGA_FME_PORT_PR, uintptr(unsafe.Pointer(&value)))
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return err
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}
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// PortRelease releases the port per Port ID provided by caller.
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// * Return: 0 on success, -errno on failure.
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func (f *IntelFpgaFME) PortRelease(port uint32) error {
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var value IntelFpgaFmePortRelease
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value.Argsz = uint32(unsafe.Sizeof(value))
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value.Id = port
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_, err := ioctlDev(f.DevPath, FPGA_FME_PORT_RELEASE, uintptr(unsafe.Pointer(&value)))
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return err
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}
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// PortAssign assigns the port back per Port ID provided by caller.
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// * Return: 0 on success, -errno on failure.
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func (f *IntelFpgaFME) PortAssign(port uint32) error {
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var value IntelFpgaFmePortAssign
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value.Argsz = uint32(unsafe.Sizeof(value))
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value.Id = port
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_, err := ioctlDev(f.DevPath, FPGA_FME_PORT_ASSIGN, uintptr(unsafe.Pointer(&value)))
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return err
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}
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// GetDevPath returns path to device node.
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func (f *IntelFpgaFME) GetDevPath() string {
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return f.DevPath
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}
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// GetSysFsPath returns sysfs entry for FPGA FME or Port (e.g. can be used for custom errors/perf items).
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func (f *IntelFpgaFME) GetSysFsPath() string {
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if f.SysFsPath != "" {
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return f.SysFsPath
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}
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sysfs, err := FindSysFsDevice(f.DevPath)
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if err != nil {
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return ""
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}
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f.SysFsPath = sysfs
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return f.SysFsPath
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}
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// GetName returns simple FPGA name, derived from sysfs entry, can be used with /dev/ or /sys/bus/platform/.
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func (f *IntelFpgaFME) GetName() string {
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if f.Name != "" {
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return f.Name
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}
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f.Name = filepath.Base(f.GetSysFsPath())
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return f.Name
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}
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// GetPCIDevice returns PCIDevice for this device.
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func (f *IntelFpgaFME) GetPCIDevice() (*PCIDevice, error) {
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if f.PCIDevice != nil {
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return f.PCIDevice, nil
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}
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pci, err := NewPCIDevice(f.GetSysFsPath())
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if err != nil {
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return nil, err
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}
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f.PCIDevice = pci
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return f.PCIDevice, nil
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}
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// GetPortsNum returns amount of FPGA Ports associated to this FME.
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func (f *IntelFpgaFME) GetPortsNum() int {
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if f.PortsNum == "" {
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err := f.updateProperties()
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if err != nil {
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return -1
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}
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}
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n, err := strconv.ParseUint(f.PortsNum, 10, 32)
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if err != nil {
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return -1
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}
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return int(n)
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}
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// GetInterfaceUUID returns Interface UUID for FME.
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func (f *IntelFpgaFME) GetInterfaceUUID() (id string) {
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if f.CompatID == "" {
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err := f.updateProperties()
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if err != nil {
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return ""
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}
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}
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return f.CompatID
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}
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// GetSocketID returns physical socket number, in case NUMA enumeration fails.
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func (f *IntelFpgaFME) GetSocketID() (uint32, error) {
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if f.SocketID == "" {
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return math.MaxUint32, errors.Errorf("n/a")
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}
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id, err := strconv.ParseUint(f.SocketID, 10, 32)
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return uint32(id), err
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}
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// GetBitstreamID returns FME bitstream id.
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func (f *IntelFpgaFME) GetBitstreamID() string {
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return f.BitstreamID
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}
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// GetBitstreamMetadata returns FME bitstream metadata.
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func (f *IntelFpgaFME) GetBitstreamMetadata() string {
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return f.BitstreamMetadata
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}
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// Update properties from sysfs.
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func (f *IntelFpgaFME) updateProperties() error {
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pci, err := f.GetPCIDevice()
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if err != nil {
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return err
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}
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fileMap := map[string]*string{
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"bitstream_id": &f.BitstreamID,
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"bitstream_metadata": &f.BitstreamMetadata,
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"dev": &f.Dev,
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"ports_num": &f.PortsNum,
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"socket_id": &f.SocketID,
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"pr/interface_id": &f.CompatID,
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}
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return readFilesInDirectory(fileMap, filepath.Join(pci.SysFsPath, intelFpgaFmeGlobPCI))
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}
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// Port interfaces
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// PortReset Reset the FPGA Port and its AFU. No parameters are supported.
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// Userspace can do Port reset at any time, e.g. during DMA or PR. But
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// it should never cause any system level issue, only functional failure
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// (e.g. DMA or PR operation failure) and be recoverable from the failure.
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// * Return: 0 on success, -errno of failure.
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func (f *IntelFpgaPort) PortReset() error {
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_, err := ioctlDev(f.DevPath, FPGA_PORT_RESET, 0)
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return err
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}
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// PortGetInfo Retrieve information about the fpga port.
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// Driver fills the info in provided struct IntelFpga_fpga_port_info.
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// * Return: 0 on success, -errno on failure.
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func (f *IntelFpgaPort) PortGetInfo() (ret PortInfo, err error) {
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var value IntelFpgaPortInfo
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value.Argsz = uint32(unsafe.Sizeof(value))
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_, err = ioctlDev(f.DevPath, FPGA_PORT_GET_INFO, uintptr(unsafe.Pointer(&value)))
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if err == nil {
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ret.Flags = value.Flags
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ret.Regions = value.Regions
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ret.Umsgs = value.Umsgs
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}
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return
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}
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// PortGetRegionInfo Retrieve information about the fpga port.
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// * Retrieve information about a device memory region.
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// * Caller provides struct IntelFpga_fpga_port_region_info with index value set.
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// * Driver returns the region info in other fields.
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// * Return: 0 on success, -errno on failure.
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func (f *IntelFpgaPort) PortGetRegionInfo(index uint32) (ret PortRegionInfo, err error) {
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var value IntelFpgaPortRegionInfo
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value.Argsz = uint32(unsafe.Sizeof(value))
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value.Index = index
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_, err = ioctlDev(f.DevPath, FPGA_PORT_GET_REGION_INFO, uintptr(unsafe.Pointer(&value)))
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if err == nil {
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ret.Flags = value.Flags
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ret.Index = value.Index
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ret.Offset = value.Offset
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ret.Size = value.Size
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}
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return
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}
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// GetDevPath returns path to device node.
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func (f *IntelFpgaPort) GetDevPath() string {
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return f.DevPath
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}
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// GetSysFsPath returns sysfs entry for FPGA FME or Port (e.g. can be used for custom errors/perf items).
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func (f *IntelFpgaPort) GetSysFsPath() string {
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if f.SysFsPath != "" {
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return f.SysFsPath
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}
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sysfs, err := FindSysFsDevice(f.DevPath)
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if err != nil {
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return ""
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}
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f.SysFsPath = sysfs
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return f.SysFsPath
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}
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// GetName returns simple FPGA name, derived from sysfs entry, can be used with /dev/ or /sys/bus/platform/.
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func (f *IntelFpgaPort) GetName() string {
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if f.Name != "" {
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return f.Name
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}
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f.Name = filepath.Base(f.GetSysFsPath())
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return f.Name
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}
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// GetPCIDevice returns PCIDevice for this device.
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func (f *IntelFpgaPort) GetPCIDevice() (*PCIDevice, error) {
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if f.PCIDevice != nil {
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return f.PCIDevice, nil
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}
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pci, err := NewPCIDevice(f.GetSysFsPath())
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if err != nil {
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return nil, err
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}
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f.PCIDevice = pci
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return f.PCIDevice, nil
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}
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// GetFME returns FPGA FME device for this port.
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func (f *IntelFpgaPort) GetFME() (fme FME, err error) {
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if f.FME != nil {
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return f.FME, nil
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}
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pci, err := f.GetPCIDevice()
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if err != nil {
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return nil, err
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}
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if pci.PhysFn != nil {
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pci = pci.PhysFn
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}
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var dev string
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fileMap := map[string]*string{
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"dev": &dev,
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}
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if err = readFilesInDirectory(fileMap, filepath.Join(pci.SysFsPath, intelFpgaFmeGlobPCI)); err != nil {
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return nil, err
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}
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realDev, err := filepath.EvalSymlinks(filepath.Join("/dev/char", dev))
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if err != nil {
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return nil, err
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}
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fme, err = NewIntelFpgaFME(realDev)
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if err != nil {
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return nil, err
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}
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f.FME = fme
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return fme, err
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}
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// GetPortID returns ID of the FPGA port within physical device.
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func (f *IntelFpgaPort) GetPortID() (uint32, error) {
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if f.ID == "" {
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err := f.updateProperties()
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if err != nil {
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return math.MaxUint32, err
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}
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}
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id, err := strconv.ParseUint(f.ID, 10, 32)
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return uint32(id), err
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}
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// GetAcceleratorTypeUUID returns AFU UUID for port.
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func (f *IntelFpgaPort) GetAcceleratorTypeUUID() string {
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err := f.updateProperties()
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if err != nil || f.AFUID == "" {
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return ""
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}
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return f.AFUID
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}
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// GetInterfaceUUID returns Interface UUID for FME.
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func (f *IntelFpgaPort) GetInterfaceUUID() (id string) {
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fme, err := f.GetFME()
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if err != nil {
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return ""
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}
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defer fme.Close()
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return fme.GetInterfaceUUID()
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}
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// PR programs specified bitstream to port.
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func (f *IntelFpgaPort) PR(bs bitstream.File, dryRun bool) error {
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return genericPortPR(f, bs, dryRun)
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}
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// Update properties from sysfs.
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func (f *IntelFpgaPort) updateProperties() error {
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fileMap := map[string]*string{
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"afu_id": &f.AFUID,
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"dev": &f.Dev,
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"id": &f.ID,
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}
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return readFilesInDirectory(fileMap, f.GetSysFsPath())
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}
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